1. Field of the Invention
This invention is related to power management in integrated circuits and systems employing integrated circuits.
2. Description of the Related Art
As the number of transistors included on an integrated circuit “chip” continues to increase, power management in the integrated circuits continues to increase in importance. Power management can be critical to integrated circuits that are included in mobile devices such as personal digital assistants (PDAs), cell phones, smart phones, laptop computers, net top computers, etc. These mobile devices often rely on battery power, and reducing power consumption in the integrated circuits can increase the life of the battery. Additionally, reducing power consumption can reduce the heat generated by the integrated circuit, which can reduce cooling requirements in the device that includes the integrated circuit (whether or not it is relying on battery power).
Clock gating is often used to reduce dynamic power consumption in an integrated circuit, disabling the clock to idle circuitry and thus preventing switching in the idle circuitry. Additionally, some integrated circuits have implemented power gating to reduce static power consumption (e.g. consumption due to leakage currents). With power gating, the power to ground path of the idle circuitry is interrupted, reducing the leakage current to near zero.
Power gating can be an effective power conservation mechanism. On the other hand, power gating reduces performance because the power-gated circuitry cannot be used until power is restored and the circuitry is initialized for use. The tradeoff between performance (especially perceived performance from the user perspective) and power conservation is complex and difficult to manage. In particular, the process of stopping a block in order to power gate the block consumes power but does not improve performance.